Yosys began as a BSc thesis project by Claire Wolf intended to support synthesisfor a CGRA (coarse-grained reconfigurable architecture). It then expanded intomore general infrastructure for research on synthesis.
Modern Yosys has full support for the synthesizable subset of Verilog-2005 andhas been described as “the GCC of hardware synthesis.” Freely available andopen source, Yosys finds use across hobbyist and commercial applications aswell as academic.
Note
Yosys is released under the ISC License:
A permissive license lets people do anything with your code with properattribution and without warranty. The ISC license is functionally equivalentto the BSD 2-Clause and MIT licenses, removing some language that is nolonger necessary.
Together with the place and route tool nextpnr, Yosys can be used to programsome FPGAs with a fully end-to-end open source flow (Lattice iCE40 and ECP5). Italso does the synthesis portion for the OpenLane flow, targeting the SkyWater130nm open source PDK for fully open source ASIC design. Yosys can also doformal verification with backends for solver formats like SMT2.
Yosys, and the accompanying Open Source EDA ecosystem, is currently maintainedby Yosys Headquarters, with many of the core developers employed by YosysHQGmbH. A commercial extension, Tabby CAD Suite, includes the Verificfrontend for industry-grade SystemVerilog and VHDL support, formal verificationwith SVA, and formal apps.
What you can do with Yosys¶
Read and process (most of) modern Verilog-2005 code
Perform all kinds of operations on netlist (RTL, Logic, Gate)
Perform logic optimizations and gate mapping with ABC
Typical applications for Yosys¶
Synthesis of final production designs
Pre-production synthesis (trial runs before investing in other tools)
Conversion of full-featured Verilog to simple Verilog
Conversion of Verilog to other formats (BLIF, BTOR, etc)
Demonstrating synthesis algorithms (e.g. for educational purposes)
Framework for experimenting with new algorithms
Framework for building custom flows (Not limited to synthesis but also formalverification, reverse engineering, …)
Things you can’t do¶
Process high-level languages such as C/C++/SystemC
Create physical layouts (place&route)
Check out nextpnr for that
The Yosys family¶
As mentioned above, YosysHQ maintains not just Yosys but an entire family oftools built around it. In no particular order:
- SBY for formal verification
Yosys provides input parsing and conversion to the formats used by the solverengines. Yosys also provides a unified witness framework for providing covertraces and counter examples for engines which don’t natively support this.SBY source | SBY docs
- EQY for equivalence checking
In addition to input parsing and preparation, Yosys provides the pluginsupport enabling EQY to operate on designs directly. EQY source | EQYdocs
- MCY for mutation coverage
Yosys is used to read the source design, generate a list of possiblemutations to maximise design coverage, and then perform selected mutations.MCY source | MCY docs
- SCY for deep formal traces
Since SCY generates and runs SBY, Yosys provides the same utility for SCY asit does for SBY. Yosys additionally provides the trace concatenation neededfor outputting the deep traces. SCY source
The original thesis abstract¶
The first version of the Yosys documentation was published as a bachelor thesisat the Vienna University of Technology [Wol13].
- Abstract:
Most of today’s digital design is done in HDL code (mostly Verilog orVHDL) and with the help of HDL synthesis tools.
In special cases such as synthesis for coarse-grain cell libraries orwhen testing new synthesis algorithms it might be necessary to write acustom HDL synthesis tool or add new features to an existing one. Inthese cases the availability of a Free and Open Source (FOSS) synthesistool that can be used as basis for custom tools would be helpful.
In the absence of such a tool, the Yosys Open SYnthesis Suite (Yosys)was developed. This document covers the design and implementation ofthis tool. At the moment the main focus of Yosys lies on the high-levelaspects of digital synthesis. The pre-existing FOSS logic-synthesis toolABC is used by Yosys to perform advanced gate-level optimizations.
An evaluation of Yosys based on real-world designs is included. It isshown that Yosys can be used as-is to synthesize such designs. Theresults produced by Yosys in this tests where successfully verifiedusing formal verification and are comparable in quality to the resultsproduced by a commercial synthesis tool.
Yosys is a Verilog HDL synthesis tool. This means that it takes a behaviouraldesign description as input and generates an RTL, logical gate or physical gatelevel description of the design as output. Yosys’ main strengths are behaviouraland RTL synthesis. A wide range of commands (synthesis passes) exist withinYosys that can be used to perform a wide range of synthesis tasks within thedomain of behavioural, rtl and logic synthesis. Yosys is designed to beextensible and therefore is a good basis for implementing custom synthesis toolsfor specialised tasks.
Benefits of open source HDL synthesis¶
Cost (also applies to
free as in free beersolutions):Today the cost for a mask set in 180nm technology is far less thanthe cost for the design tools needed to design the mask layouts. Open SourceASIC flows are an important enabler for ASIC-level Open Source Hardware.
Availability and Reproducibility:
If you are a researcher who is publishing, you want to use tools that everyoneelse can also use. Even if most universities have access to all majorcommercial tools, you usually do not have easy access to the version that wasused in a research project a couple of years ago. With Open Source tools youcan even release the source code of the tool you have used alongside your data.
Framework:
Yosys is not only a tool. It is a framework that can be used as basis for otherdevelopments, so researchers and hackers alike do not need to re-invent thebasic functionality. Extensibility was one of Yosys’ design goals.
All-in-one:
Because of the framework characteristics of Yosys, an increasing number of featuresbecome available in one tool. Yosys not only can be used for circuit synthesis butalso for formal equivalence checking, SAT solving, and for circuit analysis, toname just a few other application domains. With proprietary software one needs tolearn a new tool for each of these applications.
Educational Tool:
Proprietary synthesis tools are at times very secretive about their innerworkings. They often are
black boxes. Yosys is very open about itsinternals and it is easy to observe the different steps of synthesis.
History of Yosys¶
A Hardware Description Language (HDL) is a computer language used to describecircuits. A HDL synthesis tool is a computer program that takes a formaldescription of a circuit written in an HDL as input and generates a netlist thatimplements the given circuit as output.
Currently the most widely used and supported HDLs for digital circuits areVerilog [A+02, A+06] and VHDL[A+04, A+09]. Both HDLs are used for test and verification purposesas well as logic synthesis, resulting in a set of synthesizable and a set ofnon-synthesizable language features. In this document we only look at thesynthesizable subset of the language features.
In recent work on heterogeneous coarse-grain reconfigurable logic[WGS+12] the need for a custom application-specific HDL synthesistool emerged. It was soon realised that a synthesis tool that understood Verilogor VHDL would be preferred over a synthesis tool for a custom HDL. Given anexisting Verilog or VHDL front end, the work for writing the necessaryadditional features and integrating them in an existing tool can be estimated tobe about the same as writing a new tool with support for a minimalistic customHDL.
The proposed custom HDL synthesis tool should be licensed under a Free and OpenSource Software (FOSS) licence. So an existing FOSS Verilog or VHDL synthesistool would have been needed as basis to build upon. The main advantages ofchoosing Verilog or VHDL is the ability to synthesize existing HDL code and tomitigate the requirement for circuit-designers to learn a new language. In orderto take full advantage of any existing FOSS Verilog or VHDL tool, such a toolwould have to provide a feature-complete implementation of the synthesizable HDLsubset.
Basic RTL synthesis is a well understood field [HS96]. Lexing,parsing and processing of computer languages [ASU86] is athoroughly researched field. All the information required to write such toolshas been openly available for a long time, and it is therefore likely that aFOSS HDL synthesis tool with a feature-complete Verilog or VHDL front end mustexist which can be used as a basis for a custom RTL synthesis tool.
Due to the author’s preference for Verilog over VHDL it was decided early on togo for Verilog instead of VHDL [1]. So the existing FOSS Verilog synthesistools were evaluated. The results of this evaluation are utterly devastating.Therefore a completely new Verilog synthesis tool was implemented and isrecommended as basis for custom synthesis tools. This is the tool that isdiscussed in this document.
